美国专利US20010005056A1 Multiple seed layers for metallic interconnects

专利PDF首页>>美国专利

专利附录

专利说明

权利要求

类似技术

同族专利

引用文献

法律状态

优先权

专利摘要:
One embodiment of the present invention is a multiple seed layer structure for making metallic interconnect including: (a) a patterned insulating layer on a substrate, the patterned insulating layer including at least one opening and a field surrounding the at least one opening; (b) a barrier layer disposed over the field and inside surfaces of the at least one opening; (c) a first seed layer disposed over the barrier layer using a first deposition technique; (d) a second seed layer disposed over the first seed layer using a second deposition technique, the first and second deposition techniques being different, one producing a substantially conformal seed layer and the other producing a substantially non-conformal seed layer; and (e) an electroplated metallic layer disposed over the second seed layer, the electroplated metallic layer including a material selected from a group consisting of Cu, Ag, or alloys including one or more of these metals.
公开号:US20010005056A1
申请号:US09/730,220
申请日:2000-12-04
公开日:2001-06-28
发明作者:Uri Cohen
申请人:Uri Cohen；
IPC主号:H01L21-76843

专利说明:
[0001] This is a continuation-in-part of a patent application entitled “Seed Layers for Interconnects and Methods and Apparatus for Their Fabrication”, filed on May 3, 2000, Ser. No. 09/563,733, which itself is a continuation-in-part of a patent application Ser. No. 09/410,898, filed on Oct. 2, 1999, now U.S. Pat. No. 6,136,707 (Oct. 24, 2000). [0001] TECHNICAL FIELD OF THE INVENTION
[0002] The present invention pertains to the field of electroplating metals or alloys for filling high aspect ratio openings, such as trenches and vias, for semiconductor metallization interconnects, thin film heads, micromachined Microelectromechanical Systems (MEMS) devices, or high density integrated circuit packages. In particular, embodiments of the present invention provide improved seed layers for electroplating copper or silver interconnects in semiconductor devices, and methods and apparatus for fabricating such improved seed layers. The improved seed layers facilitate reliable, void-free filling of small openings with high aspect ratios for so called “Damascene” and “Dual Damascene” copper and/or silver interconnects. [0002] BACKGROUND OF THE INVENTION
[0003] As is well known in the prior art, filling trenches and/or vias formed on a wafer by electroplating copper metal to form semiconductor device interconnects (often referred to as a “Damascene” or a “Dual Damascene” process) requires that a metallization layer (often referred to in the art as a seed layer or a base layer) be formed over the wafer surface. As is also well known in the prior art, the seed layer is required: (a) to provide a low-resistance electrical path (to enables uniform electroplating over the wafer surface); (b) to adhere well to the wafer surface (usually to an oxide-containing a dielectric film such as SiO[0003] ₂, SiO_X, or SiO_XN_Y); and (c) to be compatible with subsequent electroplating copper thereon.
[0004] As is well known, the requirement of providing a low-resistance electrical path is fulfilled by choosing the seed layer to be comprised of an adequately thick, low-resistivity material. [0004]
[0005] As is further well known, since copper has a rather poor adhesion to oxide surfaces, the requirement of adhering well to the wafer surface is typically fulfilled by disposing an intermediary barrier (or adhesion) metallic layer having a strong affinity for oxygen atoms under the seed layer. As is well known in the prior art, the barrier metallic layer is formed prior to the seed layer to provide good adhesion: (a) to the oxide surface underneath it (the barrier layer provides good adhesion to the oxide surface by sharing oxygen atoms) and (b) to the seed layer above it (the barrier metallic layer provides good adhesion to the seed layer by metal to metal bonds). The barrier layer is often also referred to as an “adhesion layer” or a “liner”. In addition to providing good adhesion, the barrier layer also serves to mitigate copper out-diffusion directly into the device, or indirectly (through an insulating or a dielectric layer) into the device. As is well known in the prior art, the barrier layer is usually chosen from the refractory metals or their alloys, such as for example, Ta, TaN[0005] _X, Cr, CrN_X, Ti, TiN_X, W, WN_X, and other alloys containing one or more of these materials.
[0006] As is still further well known, the requirement of being compatible with electroplating copper is fulfilled by choosing a seed layer that does not react spontaneously (i.e., by displacement) with copper electrolyte used during the electroplating. This is satisfied by requiring that the seed layer does not comprise a metal or alloy that is less noble than copper. [0006]
[0007] Typically, a seed layer comprises a copper layer that is deposited by a “dry” technique, such as by physical vapor deposition (“PVD”), including but not limited to sputtering, ion plating, or evaporation, or by chemical vapor deposition (“CVD”). However, the seed layer may also be deposited by a “wet” electroless plating process. In such cases, the copper seed layer thickness is typically in a range of about 300 Å to about 2,000 Å on the field (i.e., the top surface of the wafer outside trenches and via openings). In such cases, the barrier layer is typically deposited to a thickness of about 50 Å to about 500 Å (on the field) by either a PVD or a CVD technique. [0007]
[0008] The PVD techniques include, for example and without limitation, techniques such as evaporation, ion plating, and various sputtering techniques, such as DC and/or RF plasma sputtering, bias sputtering, magnetron sputtering, or Ionized Metal Plasma (IMP) sputtering. As is well known in the art, in general, due to their anisotropic and directional (“line of sight”) nature, the PVD techniques produce non-conformal deposition. For a comprehensive description of sputtering techniques and their applications, see for example an article entitled “Sputter Deposition Processes” by R. Parsons, pp. 177-208 in [0008] Thin Film Processes II, edited by J. L. Vosen and W. Kern, Academic Press (1991). However, some of the PVD techniques (such as ion plating) may produce, under certain conditions, a relatively more conformal deposition. For a comprehensive description of the ion plating technique and its applications, see for example an article entitled “The Cathodic Arc Plasma Deposition of Thin Films” by P. C. Johnson, pp. 209-285 in Thin Film Processes II, edited by J. L. Vosen and W. Kern, Academic Press (1991). The CVD techniques include, for example and without limitation, thermal CVD, Plasma Enhanced CVD (“PECVD”), Low Pressure CVD (“LPCVD”), High Pressure CVD (“HPCVD”), and Metallo Organic CVD (“MOCVD”). For a comprehensive description of CVD techniques and their applications, see for example an article entitled “Thermal Chemical Vapor Deposition” by K. F. Jensen and W. Kern, pp. 283-368 in Thin Film Processes II, edited by J. L. Vosen and W. Kern, Academic Press (1991). For example, one precursor used for CVD Cu is Cupraselect™, which precursor is sold by Schumacher, Inc. Another precursor is Cu(II) hexafluoroacetylacetonate. The latter can be reacted with hydrogen gas to obtain high purity copper. As is well known in the art, in general, due to their isotropic and non-directional nature, the CVD and the electroless techniques produce conformal deposition, with substantially uniform thickness over the entire surface, including over the field and the bottom and sidewall surfaces of the openings.
[0009] Aspect ratio (“AR”) is typically defined as a ratio between a vertical dimension, D (depth), of an opening and its smallest lateral dimension, W (width, or diameter): AR=D/W. Usually, in electroplating metals or alloys to fill patterns having high aspect ratio openings (for example, in an insulator or a dielectric), the electroplating rate inside openings is slower than the rate outside openings (i.e., on the field). Further, the higher the AR of the openings, the slower the electroplating rate is inside. This results in poor or incomplete filling (voids) of high AR openings, when compared with results achieved with low AR openings. To overcome this problem in the prior art, commercial copper electrolytes contain additives that adsorb and locally inhibit (or suppress) growth outside the openings (i.e., on the field). Further, growth inhibition inside the openings is decreased from that achieved outside the openings due to slow replenishment of the additives inside the openings as compared with replenishment of the additives on the field. As a result, the deposition rate inside the openings is faster than outside, thereby facilitating void-free copper fill. Other well known reasons for voids in copper electrofill include discontinuous (or incomplete coverage of) seed layers inside the openings, and pinching-off of opening walls (for example, by overhangs of the top corners) prior to plating. [0009]
[0010] The openings may consist of vias, trenches, or patterned photoresist. As is well known, in damascene or dual damascene processes, an insulating or a dielectric layer is pattern-etched to form openings therein. Next, a barrier (or an adhesion) metallic layer and a seed layer are deposited over the insulating layer to metallize its field (the surface surrounding openings), as well as the sidewalls and bottom surfaces of the openings. Next, copper electroplating is performed over the entire metallized surface, including the top surface (the field) surrounding the openings, and inside the patterned openings. Finally, excess plated copper overlying the openings and the top surface (the field) of the insulating layer, as well as the barrier and seed layers on the field, are removed, for example, by a mechanical polishing or by a chemical mechanical polishing (“CMP”) technique. The end result is copper filled openings (trenches and vias), including bottom and sidewall surfaces lined by the barrier and seed layers. In today's most advanced copper filling processes for trenches and vias, the openings have ARs as high as 7:1 (D=1.4 μm; W=0.2 μm). Future trenches and vias openings will likely require W=0.10 - 0.18 μm, or narrower, and AR=8:1 - 20:1, or larger. [0010]
[0011] As semiconductor device dimensions continue to shrink, there is an ever increasing demand for narrower interconnect cross-sections and, thus, smaller openings and larger aspect ratios (AR) during the copper electrofill. To ensure void-free copper filling, the seed layer inside the openings must completely cover the bottom and the sidewall surfaces inside the openings without discontinuities, or else there will be voids in the copper electrofill. On the other hand, the seed layer must not be so thick on the sidewalls that it pinches-off the very narrow openings and should not overhang the top corners of the openings so that it pinches-off the very small openings. Similarly, the barrier layer must also be continuous inside the openings. In contrast to these requirements with respect to the openings, the seed layer must be sufficiently thick on the top surface (the field) to provide a low-resistive electrical path that facilitates uniform plating across the surface of the wafer. That is, the seed layer must be sufficiently thick (for example, a Cu seed layer should preferably be at least about 1,000 Å) on the field to avoid radial non-uniformity across the wafer caused by a voltage (or IR) drop between a contact at the edge of the wafer to the center of the wafer. Any voltage drop (and resulting non-uniformity therefrom) becomes more severe as the resistance of the seed layer increases due to high resistivity and/or insufficient thickness. To ensure a sufficiently low-resistance seed layer, it is now common to deposit a copper seed layer to a thickness of about 1,000 Å to about 2,000 Å on the top surface (field) by a PVD technique. However, the typical conformal seed layer thickness of about 300 Å to about 800 Å (on the field), deposited by the CVD or electroless techniques, may not be sufficient. [0011]
[0012] Neither of these techniques satisfies all of the above-identified requirements. The non-conformal PVD techniques, while providing adequate thickness on the field, fail to provide continuous and complete sidewall and/or bottom coverage inside very narrow openings with large AR. They also result in substantial overhangs at the top corners of the openings. The conformal CVD or electroless techniques, on the other hand, while providing continuous and complete sidewalls and bottom coverage of the seed layer inside very narrow openings, pinch-off the small openings when used at thicknesses required on the field for a low-resistance electrical path. As a result, typical conformal CVD or electroless seed layers are too thin on the field and too thick inside the very narrow openings. [0012]
[0013] As one can readily appreciate from the above, a need exists in the art for a method and apparatus to produce a continuous seed layer on the sidewalls and bottom of the openings, while maintaining sufficient thickness on the field to facilitate void-free copper electrochemical filling of very narrow openings having high aspect ratios. [0013] SUMMARY OF THE INVENTION
[0014] Embodiments of the present invention advantageously satisfy the above-identified need in the art and provide multiple seed layer structures used to produce void-free copper or silver interconnect by electrochemical filling of small openings having high aspect ratios. [0014]
[0015] One embodiment of the present invention is a multiple seed layer structure used to fabricate devices which comprises: (a) a barrier layer disposed over an opening in an insulating layer and inside surfaces of the opening; (b) a first seed layer disposed over the barrier layer, which first seed layer is formed by a first deposition technique; (c) a second seed layer disposed over the first seed layer, which second seed layer is formed by a second deposition technique, the first and second deposition techniques being different; and (d) an electroplated metallic layer disposed over the second seed layer, wherein the electroplated metallic layer comprises a material selected from a group consisting of Cu, Ag, or alloys comprising one or more of these metals. [0015] BRIEF DESCRIPTION OF THE FIGURES
[0016] FIG. 1 shows a cross-sectional view of an inventive structure formed in accordance with one embodiment of the present invention wherein a first, substantially conformal seed layer is deposited over a barrier layer, followed by a second, substantially non-conformal seed layer deposited over the first, conformal seed layer; [0016]
[0017] FIG. 2 shows a cross-sectional view of the inventive structure of FIG. 1 after removing excess plated copper or silver overlying an opening and the field, as well as removing the seed layers and barrier layer overlying the field surrounding the opening; [0017]
[0018] FIG. 3 shows a cross-sectional view of an inventive structure formed in accordance with an alternative embodiment of the present invention wherein a first, substantially non-conformal seed layer is deposited over a barrier layer, followed by a second, substantially conformal seed layer deposited over the first, non-conformal seed layer; [0018]
[0019] FIG. 4 shows a cross-sectional view of the inventive structure of FIG. 3 after removing excess plated copper or silver overlying an opening and the field, as well as removing the seed layers and barrier layer overlying the field surrounding the opening; [0019]
[0020] FIG. 5 shows a scanning electron microscope (“SEM”) photograph of a cleaved cross-section (with a tilt angle of 30°) of a trench (the trench is ˜0.10 μm wide, ˜1.4 μm deep, and has an aspect ratio of ˜14:1) having seed layers formed in accordance with one embodiment of the present invention; [0020]
[0021] FIG. 6 shows an SEM photograph of the trench shown in FIG. 5 without a tilt, and with a larger enlargement; and [0021]
[0022] FIG. 7 shows a schematic (not to scale) top view of a cluster tool apparatus, and a frontal view of its controller (e.g. computer), in accordance with other embodiments of the invention. [0022] DETAILED DESCRIPTION
[0023] FIG. 1 shows a cross-sectional view of an inventive structure formed in accordance with one embodiment of the present invention wherein a substantially conformal seed layer is deposited over a barrier layer, followed by a substantially non-conformal seed layer deposited over the substantially conformal seed layer. As defined herein, a “substantially conformal seed layer” is a layer whose thickness on the sidewalls of an opening (at about mid-depth) is about 25-100% of its thickness on the field. Similarly, a “substantially non-conformal seed layer” is defined herein as a layer whose thickness on the sidewalls of an opening (at about mid-depth) is less than about 25% of its thickness on the field. In accordance with this embodiment, the conformal seed layer provides step coverage inside the openings [0023] 16, while the non-conformal seed layer provides a low resistance electrical path over the top surface (field 14) surrounding the openings to enable uniform plating across the substrate (or wafer). As defined herein, sidewall or step coverage means continuous sidewall coverage, and conformal and non-conformal seed layers, respectively, mean substantially conformal and substantially non-conformal seed layers, respectively. To enable uniform plating, it is preferable that the thickness of the combined seed layers be at least about 1,000 Å on the field.
[0024] Narrow openings (e.g., 0.18 μm, or narrower), with large aspect ratios, require minimization of the conformal seed layer thickness. On one hand, the conformal seed layer must be sufficiently thick to ensure adequate sidewall coverage and, on the other hand, it must not be too thick, to pinch-off the opening. In such cases, in order to provide sufficient thickness of the combined seed layers on the field (this is required to provide adequate electrical conduction on the field), the thickness of the non-conformal seed layer (on the field) may need to exceed the thickness of the conformal seed layer (on the field). In wider openings, with smaller aspect ratios, the thickness of the non-conformal seed layer may, or may not, exceed the thickness of the conformal seed layer (on the field). [0024]
[0025] In accordance with this embodiment of the present invention, barrier layer [0025] 18 is deposited over the entire surface of wafer 10, including over patterned insulating layer 12 (having had opening 16 patterned therein in accordance with any one of a number of methods that are well known to those of ordinary skill in the art), using a conformal Chemical Vapor Deposition (“CVD”) technique. Although the term barrier layer is used, it should be understood by those of ordinary skill in the art that the term barrier layer includes examples wherein: (a) the barrier layer acts both as an adhesion layer and as a barrier layer; (b) a barrier layer separate from an adhesion layer is used; and (c) a multiplicity of layers is used, some acting as adhesion layers, some acting as barrier layers, or some acting as both. Further, although the term wafer is used, this also includes the term substrate as it is used in the art. Still further, although the present invention is described in the context of opening 16, in practice, a multiplicity of openings are patterned and filled in accordance with the present invention.
[0026] Advantageously, in accordance with the present invention, the use of a CVD technique to deposit barrier layer [0026] 18 ensures substantially complete and continuous coverage of the bottom and sidewall surfaces inside opening 16. However, it is within the scope of the present invention that barrier layer 18 may also be deposited using a Physical Vapor Deposition (“PVD”) technique that provides continuous bottom and sidewall coverage. In accordance with the present invention, barrier layer 18 may comprise, for example and without limitation, a material selected from Ta, TaN_X, Cr, CrN_X, Ti, TiN_X, W, WN_X, and other alloys containing one or more of these materials. Further, the thickness of barrier layer 18 can be in a range of about 30 Å to about 500 Å, and more preferably in a range of about 50 Å to about 300 Å. Since barrier layer 18 occupies a certain fraction of interconnects formed in accordance with the present invention, and since barrier layer 18 has a relatively large resistivity, its thickness should be minimized. However, the thickness of barrier layer 18 should be sufficiently large to mitigate copper out-diffusion and to provide complete bottom and sidewall coverage inside opening 16. Many CVD techniques and PVD techniques are well known to those of ordinary skill in the art for forming barrier layer 18.
[0027] Next, substantially conformal seed layer [0027] 20 is deposited over barrier layer 18. Conformal seed layer 20 can be preferably deposited by using a CVD technique, but it can also be deposited by using an electroless technique or any other substantially conformal deposition technique. Many CVD techniques and electroless techniques are well known to those of ordinary skill in the art for forming conformal seed layer 20. The thickness of conformal seed layer 20 can be in a range of about 50 Å to about 500 Å, and more preferably in a range of about 100 Å to about 300 Å. Finally, substantially non-conformal seed layer 22 is deposited over conformal seed layer 20. Non-conformal seed layer 22 can be preferably obtained using a PVD technique. Many PVD techniques are well known to those of ordinary skill in the art for forming non-conformal seed layer 22. The thickness of non-conformal seed layer 22 can be in a range of about 100 Å to about 3,000 Å, and more preferably in a range of about 500 Å to about 2,000 Å (on the field).
[0028] In accordance with the present invention, the conformal and non-conformal seed layers may comprise the same material, or they may comprise different materials. Although copper is commonly used as a seed layer, a highly conductive silver (Ag) layer can also be used. In fact, Ag has lower resistivity than that of Cu and, therefore, can be formed with a smaller thickness than that required when using Cu. Thus, conformal seed layer [0028] 20 and non-conformal seed layer 22 may comprise, for example, a material selected from Cu, Ag, or alloys comprising one or more of these metals.
[0029] Those of ordinary skill in the art will readily understand that, although the above-described structure comprises individual conformal and non-conformal seed layers [0029] 20 and 22, respectively, these individual layers may not be discernible or distinguishable from each other in the structure after complete fabrication of the seed layers, particularly if they are comprised of the same metal or alloy.
[0030] Due to the non-directional, isotropic nature of CVD deposition techniques, the thickness of the CVD layers is substantially uniform over the entire surface (i.e., conformal), including over field [0030] 14, and over bottom and sidewall surfaces inside opening 16. In reality, however, even the best conformal CVD layers are thicker over the field than inside the openings. In fact, it is quite common for CVD Cu seed layers inside openings to have a thickness of about 80% of that over the field. In addition, the thickness of a CVD barrier layer inside the openings is typically only about 50% of that over the field. Thus, even the best CVD layers exhibit some overhang at the top corners of the openings. EXAMPLE 1
[0031] The following presents an example of an embodiment of the inventive method for 0.18 μm wide vias or trenches. In accordance with this embodiment, one deposits, by a CVD technique, a barrier layer comprised of about 200 Å of TaN[0031] _Xor WN_X, then one deposits, by a CVD technique, a conformal seed layer comprised of about 300 Å of Cu, finally one deposits, by a PVD technique, a non-conformal seed layer comprised of about 900 Å of Cu (as measured on the field). This will result in a total combined (including the barrier) thickness of about 400 Å inside the openings: {Cu(PVD˜50 Å)/Cu(CVD˜250 Å)/TaN_X(CVD˜100 Å)} and a total combined Cu seed layers and barrier layer thickness of about 1,400 Å on the field: {Cu(PVD˜900 Å)/Cu(CVD˜300 Å)/TaN_X(CVD˜200 Å}. Advantageously, in accordance with the present invention, the inventive “two-step” seed layer deposition ensures a continuous seed layer having excellent step coverage, and a low-resistance electrical path on the field to ensure uniform copper plating across the wafer. It may be noted that although the combined thickness of the copper seed layers inside the openings is only about 300 Å, due to the very short distance to the field (on the order of about 1 μm), the voltage drop from the field to the inside of the openings is negligible. Thus, the combined thickness of the “two-step” seed layers inside the openings is adequate for copper plating therein. In fact, if necessary, the thickness of the “two-step” seed layers inside the openings can be further decreased (to a range from about 100 Å to about 200 Å) to enable void-free copper filling of even smaller openings (for example, below 0.10 - 0.13 μm). In the above example, the combined thicknesses of the barrier and seed layers at the sidewalls of the openings is about 400 Å on each side, thus occupying about 800 Å of the 1,800 Å opening. This leaves enough room (˜1,000 Å) to facilitate electroplating inside the opening without sealing or pinching-off of the top corners.
[0032] In accordance with a preferred embodiment of the present invention, substantially non-conformal seed layer [0032] 22 is thicker than substantially conformal seed layer 20 on the field 14.
[0033] After depositing seed layers [0033] 20 and 22 shown in FIG. 1, substrate 10 is placed in a copper electroplating bath, and electroplating is carried out in accordance with any one of a number of methods that are well known to those of ordinary skill in the art to deposit a thickness of copper sufficient to fill patterned opening 16, with some excess, and to cover field 14 surrounding opening 16. Finally, excess plated copper overlying opening 16 and overlying field 14, as well as seed layers 20 and 22 and barrier layer 18 overlying field 14, are removed using any one of a number of techniques that are well known to those of ordinary skill in the art, for example, using a mechanical polishing or a chemical mechanical polishing (CMP) technique. Other removal techniques, such as wet or dry etching techniques may also be used to remove excess plated copper overlying opening 16 and field 14, and to remove seed layers 20 and 22 and barrier metallic layer 18 overlying field 14. It should be clear to those of ordinary skill in the art that removal may also be accomplished using a combination of techniques, including those identified above.
[0034] Although the detailed description above refers to filling opening [0034] 16 by electroplating copper, it is within the scope of the present invention to electrofill opening 16 with any low resistivity material, such as a material selected from Cu, Ag, or an alloy comprising one or more of these metals. In fact, silver (Ag) has lower resistivity than that of Cu, and may be attractive for further reducing the dimensions of the interconnects.
[0035] FIG. 2 shows a cross-sectional view of the inventive structure of FIG. 1 after removing excess plated copper (or silver) [0035] 24 overlying opening 16 and field 14, and removing seed layers 20 and 22 and barrier layer 18 overlying field 14 surrounding opening 16. FIG. 2 illustrates the filling of openings (trenches and vias) with electroplated copper (or silver) 24, as well as the lining of the bottom and sidewall surfaces of opening 16 by barrier layer 18 and seed layers 20 and 22. As shown in FIG. 2, all metallic layers were removed from field 14 of insulating layer 12 which surrounds embedded electroplated copper (or silver) interconnect 24.
[0036] Those of ordinary skill in the art will readily understand that, although the above-described structure comprises metal (or alloy) layer [0036] 24 electroplated over separately deposited conformal and non-conformal seed layers 20 and 22, respectively, following the electroplating of the metallic layer 24, these individual layers may not be discernible or distinguishable from each other in the structure, particularly if they are comprised of the same metal or alloy. Thus for example, if seed layers 20 and 22 and electroplated metal 24 are comprised of Cu, they may not be discernible from each other inside the filled openings 16, or on field 14 (prior to their removal from the field).
[0037] FIG. 3 shows a cross-sectional view of an inventive structure formed in accordance with an alternative embodiment of the present invention wherein a first, substantially non-conformal seed layer is deposited over a barrier layer, followed by a second, substantially conformal seed layer deposited over the first, non-conformal seed layer. The non-conformal seed layer provides a low resistance electrical path over the top surface (field [0037] 114) surrounding the openings 116 to enable uniform plating across the substrate (or wafer), while the conformal seed layer provides continuous and complete bottom and sidewalls (or step) coverage inside the openings.
[0038] In accordance with the alternative embodiment of the inventive method of the present invention, barrier layer [0038] 118 is deposited over the entire surface of wafer 110, including over patterned insulating layer 112 (having had opening 116 patterned therein in accordance with any one of a number of methods that are well known to those of ordinary skill in the art), using a conformal Chemical Vapor Deposition (“CVD”) technique. Although the term barrier layer is used herein, it should be understood by those of ordinary skill in the art that the term barrier layer includes examples wherein: (a) the barrier layer acts both as an adhesion layer and as a barrier layer; (b) a barrier layer separate from an adhesion layer is used; and (c) a multiplicity of layers is used, some acting as adhesion layers, some acting as barrier layers, or some acting as both. Further, although the term wafer is used, this also includes the term substrate as it is used in the art. Still further, although the present invention is described in the context of opening 116, in practice, a multiplicity of openings are patterned and filled in accordance with the present invention.
[0039] Advantageously, in accordance with the present invention, the use of a CVD technique to deposit barrier layer [0039] 118 ensures complete and continuous coverage of the bottom and sidewall surfaces inside opening 116. However, it is within the scope of the present invention that barrier layer 118 may also be deposited using a Physical Vapor Deposition (“PVD”) technique that provides continuous bottom and sidewall coverage. In accordance with the present invention, barrier layer 118 may comprise, for example and without limitation, a material selected from Ta, TaN_X, Cr, CrN_X, Ti, TiN_X, W, WN_X, and other alloys containing one or more of these materials. Further, the thickness of barrier layer 118 can be in a range of about 30 Å to about 500 Å, and more preferably in a range of about 50 Å to about 300 Å. Since barrier layer 118 occupies a certain fraction of interconnects formed in accordance with the present invention, and since barrier layer 118 has a relatively large resistivity, its thickness should be minimized. However, the thickness of barrier layer 118 should be sufficiently large to mitigate copper out-diffusion and to provide complete bottom and sidewall coverage inside opening 116. Many CVD techniques and PVD techniques are well known to those of ordinary skill in the art for forming barrier layer 118.
[0040] Next, a substantially non-conformal seed layer [0040] 126 is deposited over barrier layer 118. Non-conformal seed layer 126 can be preferably obtained using a PVD technique. Many PVD techniques are well known to those of ordinary skill in the art for forming non-conformal seed layer 126. The thickness of non-conformal seed layer 126 can be in a range of about 100 Å to about 3,000 Å, and more preferably in a range of about 500 Å to about 2,000 Å (on the field). Finally, a substantially conformal seed layer 128 is deposited over non-conformal seed layer 126. Conformal seed layer 128 can be preferably obtained using a CVD or electroless technique or any other substantially conformal deposition technique. Many CVD techniques and electroless techniques are well known to those of ordinary skill in the art for forming conformal seed layer 128. The thickness of conformal seed layer 128 can be in a range of about 50 Å to about 500 Å, and more preferably in a range of about 100 Å to about 300 Å.
[0041] In accordance with a preferred embodiment of the present invention, substantially non-conformal seed layer [0041] 126 is thicker than substantially conformal seed layer 128 on the field 114.
[0042] In accordance with the present invention, the conformal and non-conformal seed layers may comprise the same material, or they may comprise different materials. Although copper is commonly used as a seed layer, a highly conductive silver (Ag) layer can also be used. Non-conformal seed layer [0042] 126 and conformal seed layer 128 may comprise, for example, a material selected from Cu, Ag, or alloys comprising one or more of these metals.
[0043] Although reference is made here to individual non-conformal and conformal seed layers [0043] 126 and 128, respectively, it should be understood by those of ordinary skill in the art that, following the deposition of these seed layers, they may not be discernible or distinguishable from each other, particularly if they are comprised of the same metal or alloy.
[0044] After depositing seed layers [0044] 126 and 128 shown in FIG. 3, substrate 110 is placed in a copper electroplating bath, and electroplating is carried out in accordance with any one of a number of methods that are well known to those of ordinary skill in the art to deposit a thickness of copper sufficient to fill patterned opening 116, with some excess, and to cover field 114 surrounding opening 116. Finally, excess plated copper overlying opening 116 and field 114 of insulating layer 112, as well as seed layers 126 and 128 and barrier layer 118 overlying field 114, are removed using any one of a number of techniques that are well known to those of ordinary skill in the art, for example, using a mechanical polishing or a chemical mechanical polishing (CMP) technique. Other removal techniques, such as wet or dry etching techniques may also be used to remove excess plated copper overlying opening 116 and field 114, and to remove seed layers 126 and 128 and barrier layer 118 overlying field 114. It should be clear to those of ordinary skill in the art that removal may also be accomplished using a combination of techniques, including those identified above.
[0045] Although the detailed description above refers to filling opening [0045] 116 by electroplating copper, it is within the scope of this invention to electrofill opening 116 with any low resistivity material, such as a material selected from Cu, Ag, or alloys comprising one or more of these metals. In fact, silver (Ag) has lower resistivity than that of Cu, and may be attractive for further reducing the dimensions of the interconnects.
[0046] FIG. 4 shows a cross-sectional view of the inventive structure of FIG. 3 after removing excess electroplated copper (or silver) [0046] 130 overlying opening 116 and field 114, and removing seed layers 126 and 128 and barrier layer 118 overlying field 114 surrounding opening 116. FIG. 4 illustrates the filling of openings (trenches and vias) with electroplated copper (or silver) 130, as well as the lining of the bottom and sidewall surfaces of opening 116 by barrier layer 118 and seed layers 126 and 128. As shown in FIG. 4, all metallic layers were removed from field 114 of insulating layer 112 which surrounds embedded electroplated copper (or silver) interconnect 130.
[0047] Although reference is made here to individual electroplated metal or alloy [0047] 130 over seed layers 126 and 128, it should be understood by those of ordinary skill in the art that, following the electroplating of metallic layer 130, the individual layers may not be discernible or distinguishable from each other, particularly if they are comprised of the same metal or alloy. Thus for example, if seed layers 126 and 128 and electroplated metal 130 are comprised of Cu, they may not be discernible from each other inside the filled openings 116, or on field 114 (prior to their removal from the field). EXAMPLE 2
[0048] FIGS. 5 and 6 show scanning electron microscope (“SEM”) photographs of a cross-section of a 0.10 μm wide trench having Cu seed layers prepared in accordance with one embodiment of the invention. In accordance with this embodiment, a pattern of trenches was formed in a SiO[0048] ₂insulating layer. The trenches were about 0.10 μm wide (at their bottom) and about 1.4 μm deep (thereby having an aspect ratio of about 14:1). Next, a barrier layer (WN_X) was deposited using a CVD technique. Next, a relatively thin, conformal Cu seed layer was deposited using a CVD technique. The barrier layer and thin, conformal Cu seed layer is seen at 501 in FIG. 6. In accordance with this embodiment, the combined thickness of the barrier and the CVD Cu seed layer was about 500 Å on the field, and about 400-500 Å on the sidewalls and bottom of the trenches. Next, a non-conformal PVD Cu seed layer having a thickness of about 1,400 Å (on the field) was deposited by sputtering. In this embodiment, the non conformal PVD Cu seed layer was applied in two steps and is seen at 510 in FIG. 6. The end result, as shown in FIGS. 5 and 6, was a combined thickness (including the barrier and the Cu seed layers) of only about 400-500 Å on the sidewalls and bottom of the trench (with excellent continuity and uniformity there), and about 1,900 Å on the field, without pinching-off of the trench. One should note that, while FIG. 5 shows the cross-section with a tilt of about 30° and an enlargement of 20,000× (thus providing also a partial view of the top surface), FIG. 6 shows the same cross-section with an enlargement of 40,000× and without a tilt. EXAMPLE 3
[0049] Similar to Example 2 above, trenches ˜0.10 μm wide (at their bottom) and ˜1.4 μm deep (thereby having an aspect ratio of ˜14:1) were formed in a SiO[0049] ₂insulating layer. Next, a barrier layer (WN_X) was deposited using a CVD technique. Next, a relatively thin, conformal Cu seed layer was deposited using a CVD technique. The combined thickness of the barrier layer and the CVD Cu layer was ˜500 Å on the field, and ˜400-500 Å on the sidewalls and bottom of the trenches. Next, a non-conformal PVD Cu seed layer having a thickness of ˜500 Å (on the field) was deposited by sputtering. The end result was a combined thickness (including the barrier layer and the Cu seed layers) of only about 400-500 Å on the sidewalls and bottom of the trenches (with excellent continuity and uniformity there), and about 1,000 Å on the field, without pinching-off the trenches.
[0050] It should be understood that the scope of the present invention is not limited to the embodiments described above with respect to FIG. 1 and FIG. 3. For example, in accordance with further embodiments of the present invention, a relatively thin (“Flash”) PVD seed layer can be deposited first, followed by a conformal CVD or electroless seed layer, and finally followed by a (relatively thick) PVD seed layer to produce three separately deposited seed layers. [0050]
[0051] Adhesion of a metallo-organic CVD (MOCVD) deposited Cu seed layer to the underlying barrier layer is rather poor, and may not be adequate for use in devices when mechanical or chemical mechanical polishing (CMP) processing follows Cu plating. In addition, when an MOCVD Cu layer is deposited directly over a barrier layer containing a refractory metal, further problems arise. In particular, the morphology, uniformity, and electrical resistivity of the MOCVD Cu layer may not be adequate for use in devices. It is believed that these problems are due to the high affinity of the refractory metal in the barrier layer to oxygen and/or carbon atoms. Specifically, during the initial stages of MOCVD Cu deposition, the refractory metal of the barrier layer spontaneously reacts with carbon or oxygen containing species (from the organic part of the metallo-organic compound) to form an oxide, carbide, or a mixed oxide-carbide interfacial layer between itself and the depositing Cu. Such an interfacial layer adversely impairs the adhesion of the MOCVD Cu layer. Cu (as well as other noble metals) does not adhere well to oxide or carbide layers, and requires a clean metal-to-metal bond in order to adhere well to another metal. Similarly, the oxide, carbide, and/or oxide-carbide interfacial layer impairs proper nucleation of the MOCVD Cu on the refractory metal barrier layer. This adversely affects the morphology, uniformity, and resistivity of the deposited MOCVD Cu seed layer. [0051]
[0052] In accordance with one embodiment of the present invention, at least an initial stage of CVD Cu deposition is carried out utilizing high purity, inorganic Cu compounds (precursors), such as, for example and without limitation, compounds containing hydrogen and/or halides such as chlorides or fluorides, which do not contain oxygen or carbon atoms. The resulting clean metal-to-metal interface between a barrier layer containing a refractory metal and the depositing copper ensures good adhesion, morphology, uniformity, and low electrical resistivity of the CVD Cu layer. In a further embodiment, the entire CVD Cu layer can be deposited using the inorganic precursors. In a still further embodiment, only the initial stage of the CVD Cu is carried out using inorganic precursors, switching later to an MOCVD Cu deposition process, to form the rest of the CVD Cu layer. [0052]
[0053] In another embodiment of the invention, an electroless deposited metal or alloy is first deposited on the barrier layer, followed by the CVD Cu seed layer. In another embodiment, following the deposition of the electroless metal or alloy on the barrier layer, a PVD Cu seed layer is deposited directly on the electroless deposited metal or alloy. The electroless deposited metal or alloy may comprise a material selected from the group consisting of electroless deposited Cu, Au, Ag, Ni, Co, or an alloy comprising one or more of these metals. The thickness of this electroless deposited metal or alloy can be in the range of 10-500 Å, and more preferably be in the range of 25-100 Å. [0053]
[0054] In accordance with yet another embodiment of the present invention that solves the problems involved with the deposition of an MOCVD Cu layer on a barrier layer containing a refractory metal, a first, relatively thin, “Flash” PVD seed layer is deposited to enhance adhesion to the barrier layer and/or to improve grain morphology and uniformity of a subsequently deposited CVD seed layer. [0054]
[0055] Exposure of wafers to the atmosphere during transport from one deposition chamber to another may cause deleterious oxidation and/or contamination of the surface of barrier and/or seed layers. Such exposure should, therefore, be avoided or minimized. [0055]
[0056] In accordance with one embodiment of the present invention, conformal and non-conformal seed layers are deposited in an apparatus where the conformal and non-conformal seed layer deposition steps can be carried out without breaking vacuum, or without exposing the wafer to the atmosphere between the deposition steps. In accordance with this embodiment, the apparatus may comprise two or more chambers, at least one chamber for deposition of the conformal seed layer, and at least another chamber for deposition of the non-conformal seed layer. In a preferred embodiment of the present invention, the apparatus further comprises a chamber for deposition of the barrier layer, preferably by a CVD technique. The barrier layer may be deposited in a separate chamber or it may be deposited in one of the chambers used to deposit either the conformal, or the non-conformal, seed layers. [0056]
[0057] FIG. 7 shows apparatus [0057] 7000 that is fabricated in accordance with a preferred embodiment of the invention. As shown in FIG. 7, apparatus 7000 comprises cluster tool 70 which operates in accordance with input from controller 80 in a manner that is well known to those of ordinary skill in the art. As further shown in FIG. 7, cluster tool 70 includes input loadlock 71 and output loadlock 72. As is well known to those of ordinary skill in the art, loadlocks 71 and 72 enable wafers to be inserted into and removed from cluster tool 70, respectively. Although FIG. 7 shows separate input and output loadlocks, it is also within the spirit and scope of the present invention to use a single loadlock for both input and output of wafers.
[0058] As is well known to those of ordinary skill in the art, once wafer [0058] 74 is inserted into transfer chamber 73 of cluster tool 70, it can be transferred between the various processing chambers (for example, processing chambers 75-79) without breaking vacuum, or without exposure to the atmosphere. As is shown in FIG. 7, cluster tool 70 comprises CVD barrier layer deposition chamber 76, PVD Cu seed layer deposition chamber 77, and CVD Cu seed layer deposition chamber 78. In addition, FIG. 7 shows several other processing chambers, for example, processing chambers 75 and 79, which can be used for other processing steps that are well known to those of ordinary skill in the art, such as pre-cleaning, cooling, or as extra deposition chambers. Although FIG. 7 shows separate CVD chambers for depositing a barrier layer and Cu seed layers, it is also within the scope of the invention to deposit both types of layers in the same CVD chamber.
[0059] Controller [0059] 80 is apparatus which is well known to those of ordinary skill in the art, that is used to control the operation of cluster tool 70. As such, controller 80 determines the sequence and duration of movements and stays of wafer 74: (a) to and from loadlocks 71 and 72; and (b) to and from the various processing chambers 75-79. As is also well known to those of ordinary skill in the art, controller 80 controls the specific process sequence and process parameters for operation of the various ones of processing chambers 75-79, sometimes referred to in the art as “recipes.” For example, in PVD Cu seed layer deposition chamber 77, among other things, controller 80 controls the duration of the sputter deposition, the background pressure, the sputtering gas (such as Argon) pressure and flow rate, the cathodic voltage and power, and/or bias voltage applied to the wafer. Lastly, as is also well known to those of ordinary skill in the art, controller 80 performs these functions in accordance with specific recipes which are data structures that dictate the operation of controller 80 software. The data structures are typically stored on computer readable media that are input to controller 80 under the control of operation software, which operation software itself is typically stored on a computer readable medium. In accordance with a preferred embodiment of the present invention, recipes are input to controller 80 to cause it to control cluster tool 70 to process wafers in the manner described above to deposit a barrier layer and Cu seed layers without breaking vacuum or exposing a wafer to the atmosphere.
[0060] In one embodiment of the present invention, the apparatus comprises a chamber in which both conformal and non-conformal seed layers are deposited utilizing: (a) two or more distinct steps, wherein the deposition variables (or conditions or parameters) during the first step are suitable for the deposition of a substantially conformal (or a non-conformal) seed layer, and the deposition conditions during the second step are suitable for the deposition of a substantially non-conformal (or a conformal) seed layer; (b) wherein at least one of the deposition variables is varied (or ramped) continuously or gradually, thereby changing the nature of the seed layer from substantially conformal to substantially non-conformal, or vice versa; or (c) a combination of at least one distinct step of depositing a substantially conformal (or a non-conformal) seed layer and at least one gradual variation (or ramping) of at least one deposition variable towards a substantially non-conformal (or a conformal) seed layer, and vice versa. [0060]
[0061] As is well known to those of ordinary skill in the art, the nature of certain deposition techniques, such as ion plating or other PVD techniques, can be made more conformal, or less conformal, by varying the deposition parameters (or variables, or conditions). For example, increasing the (partial) pressure during ion plating and other PVD techniques, tends to increase scattering of the depositing atoms (or ions), thereby making the deposition more isotropic and conformal. Similarly, biasing the substrate has an effect on the nature of the deposit. For example, in ionized metal plasma (IMP) and ion plating, increasing the (negative) bias voltage further accelerates positive ions (of the depositing metal) towards the substrate, thereby improving the filling of small openings. At the same time, the higher (negative) bias also increases the removal rate (or backsputtering) from the top corners of the openings and the field, thereby rendering the deposition to be more conformal. Conversely, decreasing the negative bias, or even using positive bias, can render the deposition to be less conformal. Deposition rate (or power density) can also affect the nature of the deposition. [0061]
[0062] Similarly, as is known to those of ordinary skill in the art, the nature of certain CVD techniques can be made less conformal, or more conformal, by changing the deposition variables. For example, increasing the substrate temperature tends to shift the deposition from a surface-reaction, rate-controlled deposition at low temperature, to a transport, rate-controlled deposition at higher temperature. As a result, increasing the substrate temperature tends to render the deposition to be less conformal. Conversely, decreasing the temperature, tends to render the deposition to be more conformal. Similarly, increasing the precursor and/or the reacting gas partial pressure (or flow rate) tends to shift the deposition to be a more surface-reaction, rate-controlled deposition, thereby tending to render the deposition to be more conformal. Conversely, decreasing the partial pressure and/or flow rate of the precursor and/or a reacting gas, tends to render the deposition to be a more transport, rate-controlled deposition and, therefore, less conformal. The plasma variables in PECVD, such as the power density, may also have significant effects on the nature of the deposition. [0062]
[0063] In accordance with one embodiment of the present invention, cluster tool [0063] 70 comprises the following chambers: a CVD deposition chamber for depositing a barrier layer (for example, Ta, TaN_X, W, or WN_X); a PVD deposition chamber for depositing a PVD Cu seed layer; and a CVD deposition chamber for depositing a CVD Cu seed layer. Single wafers are transferred in-situ in cluster tool 70, from one chamber to another, without exposing the wafers to the atmosphere prior to the deposition of the top Cu seed layer. The CVD barrier and the CVD Cu seed layers can be deposited in the same CVD chamber by using different gases and chemistries for the respective layers. However, a separate CVD chamber for each layer (i.e., the barrier and the CVD Cu layers) is preferred in order to minimize cross-contamination. Using cluster tool 70, cluster tool controller 80 would cause a deposition process such as the following to be carried out in accordance with a recipe specified, for example in the form of a data structure or software or program code: (a) (in accordance with a first portion of the data structure or a first portion of the software or computer code) introducing wafer 74 into CVD barrier layer deposition chamber 76 and depositing on wafer 74 a CVD barrier layer (about 200-400 Å thick) comprising TaN_Xor WN_X; (b) (in accordance with a second portion of the data structure or a first portion of software or computer code) transferring wafer 74 through transfer chamber 73, without exposing wafer 74 to the atmosphere, to PVD Cu seed layer deposition chamber 77 and depositing on wafer 74 a relatively thin (about 100-500 Å) “Flash” PVD Cu layer; (c) (in accordance with a third portion of the data structure or a first portion of software or computer code) transferring wafer 74 through transfer chamber 73, without exposing wafer 74 to the atmosphere, to CVD Cu seed layer deposition chamber 78 and depositing on wafer 74 a CVD Cu layer (about 100-500 Å thick); and (d) (in accordance with a fourth portion of the data structure or a first portion of software or computer code) transferring wafer 74 through transfer chamber 73, without exposing it to the atmosphere, to PVD Cu seed layer deposition chamber 77 and depositing on wafer 74 a relatively thick PVD Cu layer (about 500-2,000 Å thick). Other ancillary steps include introducing wafer 74 into and removing wafer 74 from cluster tool 70 through loadlocks 71 and 72, respectively.
[0064] Another embodiment of a three-step combination may include a first deposited CVD seed layer, followed by a relatively thick PVD seed layer, and finally followed by a second deposited CVD seed layer. Other combinations may comprise even more steps in the deposition of the seed layer. In this embodiment, the three (or more) separately deposited seed layers may comprise the same metal or alloy or they may comprise, for example and without limitation, different materials chosen from Cu, Ag, or alloys comprising one or more of these metals. [0064]
[0065] It should be understood that the above-described embodiments can be used to fabricate any number of devices including, and without limitation, metallic interconnects in semiconductor devices, thin film heads, micromachined Microelectromechanical Systems (MEMS) devices, or interconnects in high density integrated circuit packages. [0065]
[0066] Although the description of the embodiments above has concentrated on metallic interconnect structures used to fabricate a device such as a semiconductor integrated circuit, these embodiments can also be used in the fabrication of other devices, such as thin film heads, micromachined Microelectromechanical Systems (MEMS) devices, or interconnects in high density integrated circuit packages. [0066]
[0067] Those skilled in the art will recognize that the foregoing description has been presented for the sake of illustration and description only. As such, it is not intended to be exhaustive or to limit the invention to the precise form disclosed. [0067]

权利要求:
Claims (57)
[1" id="US-20010005056-A1-CLM-00001] 1. A multiple seed layer structure used to fabricate devices, said multiple seed layer structure comprises:
a substrate;
a patterned insulating layer formed on said substrate, said patterned insulating layer including at least one opening and a top field surface surrounding said at least one opening;
a barrier layer disposed over said patterned insulating layer including over inside bottom and sidewalls surfaces of the at least one opening;
a first seed layer disposed over the barrier layer, said first seed layer is formed by a first deposition technique;
a second seed layer disposed over the first seed layer, said second seed layer is formed by a second deposition technique, the first and second deposition techniques being different; and
an electroplated metallic layer disposed over the second seed layer, wherein the electroplated metallic layer comprises a material selected from a group consisting of Cu, Ag, or alloys comprising one or more of these metals.
[2" id="US-20010005056-A1-CLM-00002] 2. The multiple seed layer structure of
claim 1 wherein the first deposition technique comprises a substantially conformal deposition technique and the second deposition technique comprises a substantially non-conformal deposition technique.
[3" id="US-20010005056-A1-CLM-00003] 3. The multiple seed layer structure of
claim 2 wherein said second seed layer being thicker than said first seed layer over the field.
[4" id="US-20010005056-A1-CLM-00004] 4. The multiple seed layer structure of
claim 1 wherein the first deposition technique comprises a chemical vapor deposition or electroless deposition technique and the second deposition technique comprises a physical vapor deposition technique.
[5" id="US-20010005056-A1-CLM-00005] 5. The multiple seed layer structure of
claim 4 wherein the first deposition technique comprises a chemical vapor deposition technique.
[6" id="US-20010005056-A1-CLM-00006] 6. The multiple seed layer structure of
claim 4 wherein said second seed layer being thicker than said first seed layer over the field.
[7" id="US-20010005056-A1-CLM-00007] 7. The multiple seed layer structure of
claim 1 wherein the first deposition technique comprises a substantially non-conformal deposition technique and the second deposition technique comprises a substantially conformal deposition technique.
[8" id="US-20010005056-A1-CLM-00008] 8. The multiple seed layer structure of
claim 7 wherein said first seed layer being thicker than said second seed layer over the field.
[9" id="US-20010005056-A1-CLM-00009] 9. The multiple seed layer structure of
claim 1 wherein the first deposition technique comprises a physical vapor deposition technique and the second deposition technique comprises a chemical vapor deposition technique or electroless deposition technique.
[10" id="US-20010005056-A1-CLM-00010] 10. The multiple seed layer structure of
claim 9 wherein the second deposition technique comprises a chemical vapor deposition technique.
[11" id="US-20010005056-A1-CLM-00011] 11. The multiple seed layer structure of
claim 9 wherein said first seed layer being thicker than said second seed layer over the field.
[12" id="US-20010005056-A1-CLM-00012] 12. The multiple seed layer structure of
claim 1 wherein the electroplated metallic layer comprises Cu.
[13" id="US-20010005056-A1-CLM-00013] 13. The multiple seed layer structure of
claim 1 wherein the electroplated metallic layer comprises Ag.
[14" id="US-20010005056-A1-CLM-00014] 14. The multiple seed layer structure of claim I wherein the first and second seed layers comprise a material selected from a group consisting of Cu, Ag, or alloys comprising one or more of these metals.
[15" id="US-20010005056-A1-CLM-00015] 15. The multiple seed layer structure of
claim 1 wherein the first and second seed layers comprise Cu.
[16" id="US-20010005056-A1-CLM-00016] 16. The multiple seed layer structure of
claim 1 wherein the barrier layer is selected from a group consisting of Ta, TaN_X, Cr, CrN_X, Ti, TiN_X, W, WN_X, or alloys comprising one or more of these materials.
[17" id="US-20010005056-A1-CLM-00017] 17. The multiple seed layer structure of
claim 1 wherein the barrier layer is deposited by a chemical vapor deposition technique.
[18" id="US-20010005056-A1-CLM-00018] 18. The multiple seed layer structure of
claim 1 wherein the barrier layer is deposited by a physical vapor deposition technique.
[19" id="US-20010005056-A1-CLM-00019] 19. The multiple seed layer structure of
claim 1 wherein the first deposition technique comprises a substantially conformal deposition technique and the second deposition technique comprises a substantially non-conformal deposition technique and further comprising at least one additional seed layer deposited over the second seed layer prior to electroplating.
[20" id="US-20010005056-A1-CLM-00020] 20. The multiple seed layer structure of
claim 1 wherein the first deposition technique comprises a substantially conformal deposition technique and the second deposition technique comprises a substantially non-conformal deposition technique and further comprising at least one additional seed layer deposited under the first seed layer.
[21" id="US-20010005056-A1-CLM-00021] 21. The multiple seed layer structure of
claim 19 wherein the at least one additional seed layer is formed by a substantially conformal deposition technique.
[22" id="US-20010005056-A1-CLM-00022] 22. The multiple seed layer structure of
claim 20 wherein the at least one additional seed layer is formed by a substantially non-conformal deposition technique.
[23" id="US-20010005056-A1-CLM-00023] 23. The multiple seed layer structure of
claim 21 wherein the first deposition technique comprises a chemical vapor deposition technique, the second deposition technique comprises a physical vapor deposition technique, and the at least one additional seed layer is formed by a chemical vapor deposition technique.
[24" id="US-20010005056-A1-CLM-00024] 24. The multiple seed layer structure of
claim 22 wherein the at least one additional seed layer is formed by a physical vapor deposition technique.
[25" id="US-20010005056-A1-CLM-00025] 25. The multiple seed layer structure of
claim 1 wherein the first deposition technique comprises a substantially non-conformal deposition technique and the second deposition technique comprises a substantially conformal deposition technique and further comprising at least one additional seed layer formed over the second seed layer prior to electroplating.
[26" id="US-20010005056-A1-CLM-00026] 26. The multiple seed layer structure of
claim 25 wherein the at least one additional seed layer is formed by a substantially non-conformal deposition technique.
[27" id="US-20010005056-A1-CLM-00027] 27. The multiple seed layer structure of
claim 26 wherein the first deposition technique comprises a physical vapor deposition technique, the second deposition technique comprises a chemical vapor deposition technique, and the at least one additional seed layer is formed by a physical vapor deposition technique.
[28" id="US-20010005056-A1-CLM-00028] 28. A metallic interconnect fabricated by using the multiple seed layer structure of
claim 1 , wherein the electroplated metallic layer overlying the opening and overlying the field, and the first and second seed layers overlying the field, and the barrier layer overlying the field, are substantially removed by a removal technique, said removal technique comprises one or more of a mechanical polishing technique, a chemical mechanical polishing technique, a wet etching technique, and a dry etching technique.
[29" id="US-20010005056-A1-CLM-00029] 29. The metallic interconnect of
claim 28 wherein the first deposition technique comprises a substantially conformal deposition technique and the second deposition technique comprises a substantially non-conformal deposition technique.
[30" id="US-20010005056-A1-CLM-00030] 30. The metallic interconnect of
claim 29 wherein said second seed layer being thicker than said first seed layer over the field.
[31" id="US-20010005056-A1-CLM-00031] 31. The metallic interconnect of
claim 28 wherein:
the first deposition technique comprises a chemical vapor deposition (CVD) technique or an electroless technique; and
the second deposition technique comprises a physical vapor deposition (PVD) technique.
[32" id="US-20010005056-A1-CLM-00032] 32. The metallic interconnect of
claim 31 wherein the first deposition technique comprises a chemical vapor deposition (CVD) technique.
[33" id="US-20010005056-A1-CLM-00033] 33. The metallic interconnect of
claim 31 wherein said second seed layer being thicker than said first seed layer over the field.
[34" id="US-20010005056-A1-CLM-00034] 34. The metallic interconnect of
claim 28 wherein the first deposition technique comprises a substantially non-conformal deposition technique and the second deposition technique comprises a substantially conformal deposition technique.
[35" id="US-20010005056-A1-CLM-00035] 35. The metallic interconnect of
claim 34 wherein said first seed layer being thicker than said second seed layer over the field.
[36" id="US-20010005056-A1-CLM-00036] 36. The metallic interconnect of
claim 28 wherein:
the first deposition technique comprises a physical vapor deposition (PVD) technique; and
the second deposition technique comprises a chemical vapor deposition (CVD) or an electroless technique.
[37" id="US-20010005056-A1-CLM-00037] 37. The metallic interconnect of
claim 36 wherein the second deposition technique comprises a chemical vapor deposition (CVD) technique.
[38" id="US-20010005056-A1-CLM-00038] 38. The metallic interconnect of
claim 36 wherein said first seed layer being thicker than said second seed layer over the field.
[39" id="US-20010005056-A1-CLM-00039] 39. The metallic interconnect of
claim 29 wherein the first seed layer and the second seed layer comprise a material selected from a group consisting of Cu, Ag, or alloys comprising one or more of these metals.
[40" id="US-20010005056-A1-CLM-00040] 40. The metallic interconnect of
claim 34 wherein the first seed layer and the second seed layer comprise a material selected from a group consisting of Cu, Ag, or alloys comprising one or more of these metals.
[41" id="US-20010005056-A1-CLM-00041] 41. The metallic interconnect of
claim 29 wherein the first and second seed layers comprise Cu.
[42" id="US-20010005056-A1-CLM-00042] 42. The metallic interconnect of
claim 34 wherein the first and second seed layers comprise Cu.
[43" id="US-20010005056-A1-CLM-00043] 43. The metallic interconnect of
claim 33 wherein the first seed layer has a thickness in a range of about 50 Å to about 500 Å over the field and the second seed layer has a thickness in a range of about 100 Å to about 2,000 Å over the field.
[44" id="US-20010005056-A1-CLM-00044] 44. The metallic interconnect of
claim 33 wherein the first seed layer has a thickness in a range of about 100 Å to about 300 Å over the field and the second seed layer has a thickness in a range of about 300 Å to about 1,000 Å over the field.
[45" id="US-20010005056-A1-CLM-00045] 45. The metallic interconnect of
claim 38 wherein the first seed layer has a thickness in a range of about 100 Å to about 2,000 Å over the field and the second seed layer has a thickness in a range of about 50 Å to about 500 Å over the field.
[46" id="US-20010005056-A1-CLM-00046] 46. The metallic interconnect of
claim 38 wherein the first seed layer has a thickness in a range of about 300 Å to about 1,000 Å over the field and the second seed layer has a thickness in a range of about 100 Å to about 300 Å over the field.
[47" id="US-20010005056-A1-CLM-00047] 47. The metallic interconnect of
claim 28 wherein the barrier layer is selected from a group consisting of Ta, TaN_X, Cr, CrN_X, Ti, TiN_X, W, WN_X, or alloys comprising one or more of these materials.
[48" id="US-20010005056-A1-CLM-00048] 48. The metallic interconnect of
claim 28 wherein the barrier layer is deposited by a chemical vapor deposition technique.
[49" id="US-20010005056-A1-CLM-00049] 49. The metallic interconnect of
claim 28 wherein the barrier layer is deposited by a physical vapor deposition technique.
[50" id="US-20010005056-A1-CLM-00050] 50. The metallic interconnect of
claim 28 wherein the barrier layer has a thickness in a range of about 30 Å to about 500 Å.
[51" id="US-20010005056-A1-CLM-00051] 51. The metallic interconnect of
claim 28 wherein the barrier layer has a thickness in a range of about 50 Å to about 300 Å.
[52" id="US-20010005056-A1-CLM-00052] 52. A multiple seed layer structure used to fabricate copper interconnects, said multiple seed layer structure comprising:
a patterned insulating layer formed on a substrate, the patterned insulating layer including at least one opening and a field surrounding the at least one opening;
a barrier layer deposited over the patterned insulating layer including overlying the field and inside surfaces of the at least one opening, the barrier layer comprising a refractory metal or an alloy comprising a refractory metal;
a first copper seed layer, formed by chemical vapor deposition, disposed over the barrier layer, the first copper seed layer substantially continuously covering inside surfaces of the at least one opening;
a second copper seed layer, formed by physical vapor deposition, disposed over the first copper seed layer, said second seed layer being thicker than said first seed layer over the field; and
electroplated copper over the second seed layer.
[53" id="US-20010005056-A1-CLM-00053] 53. A multiple seed layer structure used to fabricate copper interconnects, said multiple seed layer structure comprising:
a patterned insulating layer formed over a substrate, the patterned insulating layer including at least one opening and a field surrounding the at least one opening;
a barrier layer formed over the patterned insulating layer including overlying the field and inside surfaces of the at least one opening, the barrier layer comprising a refractory metal or an alloy comprising a refractory metal;
a first copper seed layer, formed by physical vapor deposition, disposed over the barrier layer;
a second copper seed layer, formed by chemical vapor deposition, disposed over the first copper seed layer, the second copper seed layer substantially continuously covering inside surfaces of the at least one opening, said first seed layer being thicker than said second seed layer over the field; and
electroplated copper over the second seed layer.
[54" id="US-20010005056-A1-CLM-00054] 54. A multiple seed layer structure used to fabricate metallic interconnects, said multiple seed layer structure comprising:
a patterned insulating layer formed on a substrate, the patterned insulating layer including at least one opening and a field surrounding the at least one opening;
a barrier layer formed over the field and inside surfaces of the at least one opening;
two or more seed layers deposited over the barrier layer using two or more different deposition techniques; and
an electroplated metallic layer formed over the two or more seed layers, the electroplated metallic layer comprising a material selected from a group consisting of Cu, Ag, or alloys comprising one or more of these metals.
[55" id="US-20010005056-A1-CLM-00055] 55. A metallic filled via or trench interconnect fabricated by using a multiple seed layer structure, said multiple seed layer structure comprising:
a patterned insulating layer formed on a substrate, the patterned insulating layer including at least one opening and a field surrounding the at least one opening;
a barrier layer disposed over the patterned insulating layer, including inside surfaces of the at least one opening;
a substantially conformal seed layer disposed over the barrier layer, including inside surfaces of the at least one opening, said substantially conformal seed layer comprises a material selected from the group consisting of Cu, Ag, or alloys comprising one or more of these metals;
a substantially non-conformal seed layer disposed over the substantially conformal seed layer, said substantially non-conformal seed layer comprises a material selected from the group consisting of Cu, Ag, or alloys comprising one or more of these metals, said substantially non-conformal seed layer being thicker than said substantially conformal seed layer over the field; and
an electroplated metallic layer deposited over the substantially non-conformal seed layer, said electroplated metallic layer comprising a material selected from a group consisting of Cu, Ag, or alloys comprising one or more of these metals.
[56" id="US-20010005056-A1-CLM-00056] 56. A metallic filled via or trench interconnect fabricated by using a multiple seed layer structure, said multiple seed layer structure comprising:
a patterned insulating layer formed on a substrate, the patterned insulating layer including at least one opening and a field surrounding the at least one opening;
a barrier layer disposed over the patterned insulating layer, including inside surfaces of the at least one opening;
a substantially non-conformal seed layer disposed over the barrier layer, said substantially non-conformal seed layer comprises a material selected from the group consisting of Cu, Ag, or alloys comprising one or more of these metals;
a substantially conformal seed layer disposed over the substantially non-conformal seed layer, said substantially conformal seed layer comprises a material selected from the group consisting of Cu, Ag, or alloys comprising one or more of these metals, said substantially non-conformal seed layer being thicker than said substantially conformal seed layer over the field; and
an electroplated metallic layer deposited over the substantially conformal seed layer, said electroplated metallic layer comprising a material selected from a group consisting of Cu, Ag, or alloys comprising one or more of these metals.
[57" id="US-20010005056-A1-CLM-00057] 57. A metallic interconnect, said metallic interconnect comprises:
a barrier layer disposed over an opening in an insulating layer including over inside bottom and sidewall surfaces of the opening;
a first seed layer disposed over the barrier layer, which first seed layer is formed by a first deposition technique;
a second seed layer disposed over the first seed layer, which second seed layer is formed by a second deposition technique, the first and second deposition techniques being different; and
an electroplated metallic layer disposed over the second seed layer, wherein the electroplated metallic layer comprises a material selected from a group consisting of Cu, Ag, or alloys comprising one or more of these metals.

类似技术:

公开号 | 公开日 | 专利标题

US10096547B2|2018-10-09|Metallic interconnects products

US6518668B2|2003-02-11|Multiple seed layers for metallic interconnects

US6924226B2|2005-08-02|Methods for making multiple seed layers for metallic interconnects

US6136707A|2000-10-24|Seed layers for interconnects and methods for fabricating such seed layers

US6207222B1|2001-03-27|Dual damascene metallization

US7470612B2|2008-12-30|Method of forming metal wiring layer of semiconductor device

US7645696B1|2010-01-12|Deposition of thin continuous PVD seed layers having improved adhesion to the barrier layer

US20060076244A1|2006-04-13|Barrier enhancement process for copper interconnects

US20020068427A1|2002-06-06|Single step process for blanket-selective cvd aluminum deposition

EP0818817A2|1998-01-14|Aluminium hole filling using ionized metal adhesion layer

JP2002110783A|2002-04-12|Semiconductor substrate, manufacturing method of the same and semiconductor device

同族专利:

公开号 | 公开日

US6903016B2|2005-06-07|

US20040087171A1|2004-05-06|

WO2001026145A1|2001-04-12|

US6610151B1|2003-08-26|

US9673090B2|2017-06-06|

US7199052B2|2007-04-03|

US20090239372A1|2009-09-24|

US7550386B2|2009-06-23|

US20050148172A1|2005-07-07|

US7282445B2|2007-10-16|

WO2001026145A9|2002-08-15|

JP2003511858A|2003-03-25|

US20080026569A1|2008-01-31|

TW504795B|2002-10-01|

KR20020043604A|2002-06-10|

US20070117379A1|2007-05-24|

US6518668B2|2003-02-11|

US20090233440A1|2009-09-17|

引用文献:

公开号 | 申请日 | 公开日 | 申请人 | 专利标题

US6368954B1|2000-07-28|2002-04-09|Advanced Micro Devices, Inc.|Method of copper interconnect formation using atomic layer copper deposition|

US20020175423A1|2001-02-08|2002-11-28|Leonard Forbes|High performance silicon contact for flip chip|

US6503824B1|2001-10-12|2003-01-07|Mosel Vitelic, Inc.|Forming conductive layers on insulators by physical vapor deposition|

US6593236B2|2000-06-20|2003-07-15|Hynix Semiconductor Inc.|Method of forming a metal wiring in a semiconductor device with copper seed|

US20050009336A1|2003-07-07|2005-01-13|Jung-Hun Seo|Metal deposition apparatus used in fabrication of semiconductor devices and methods of forming metal layers using the same|

EP1867436A1|2005-03-09|2007-12-19|IHI Corporation|Jig|

US20080081474A1|2006-09-29|2008-04-03|Tokyo Electron Limited|Integration of a variable thickness copper seed layer in copper metallization|

CN100412607C|2003-09-29|2008-08-20|松下电器产业株式会社|Microelectromechanical system and method for fabricating the same|

US20090148677A1|2007-12-10|2009-06-11|International Business Machines Corporation|High aspect ratio electroplated metal feature and method|

US20090321936A1|2006-07-20|2009-12-31|Tokyo Electron Limited|Semiconductor device manufacturing method, semiconductor device manufacturing apparatus, semiconductor device, computer program and storage medium|

US20100140099A1|2005-01-25|2010-06-10|Taiwan Semiconductor Manufacturing Company, Ltd.|Method and apparatus for electrochemical plating semiconductor wafers|

US20100317248A1|2009-06-12|2010-12-16|Woongjin Chemical Co., Ltd.|Fabric including low-melting fiber|

US20120196437A1|2011-01-27|2012-08-02|Tokyo Electron Limited|Methods of forming copper wiring and copper film, and film forming system|

US20130140688A1|2011-12-02|2013-06-06|Chun-Hung Chen|Through Silicon Via and Method of Manufacturing the Same|

US20170005038A1|2015-06-30|2017-01-05|Taiwan Semiconductor Manufacturing Co., Ltd.|Cvd metal seed layer|

US9768060B2|2014-10-29|2017-09-19|Applied Materials, Inc.|Systems and methods for electrochemical deposition on a workpiece including removing contamination from seed layer surface prior to ECD|US147104A||1874-02-03||Improvement in machines for making cotton-laps |

US110147A||1870-12-13||Improvement in side-saddle trees |

US57527A||1866-08-28||Bronzing-machine |

US129828A||1872-07-23||Improvement in lamps |

US157431A||1874-12-01||Improvement in bottle-stoppers |

US188850A||1877-03-27||Improvement in clothes-pounders |

US121608A||1871-12-05||Improvement in animal-traps |

US241321A||1881-05-10||Charles h |

US116427A||1871-06-27||Improvement in dentists and barbers chairs |

US45485A||1864-12-20||Improved car-replacer |

US140196A||1873-06-24||Abbaham t |

JP2856782B2|1989-10-12|1999-02-10|レール・リキード・ソシエテ・アノニム・プール・レテユード・エ・レクスプロワタシオン・デ・プロセデ・ジョルジュ・クロード|Method of forming copper thin film by low temperature CVD|

US5219787A|1990-07-23|1993-06-15|Microelectronics And Computer Technology Corporation|Trenching techniques for forming channels, vias and components in substrates|

US5173442A|1990-07-23|1992-12-22|Microelectronics And Computer Technology Corporation|Methods of forming channels and vias in insulating layers|

US5151168A|1990-09-24|1992-09-29|Micron Technology, Inc.|Process for metallizing integrated circuits with electrolytically-deposited copper|

US5612254A|1992-06-29|1997-03-18|Intel Corporation|Methods of forming an interconnect on a semiconductor substrate|

US5403620A|1992-10-13|1995-04-04|Regents Of The University Of California|Catalysis in organometallic CVD of thin metal films|

CA2082771C|1992-11-12|1998-02-10|Vu Quoc Ho|Method for forming interconnect structures for integrated circuits|

JP2616402B2|1993-10-18|1997-06-04|日本電気株式会社|Method for manufacturing semiconductor device|

US5549808A|1995-05-12|1996-08-27|International Business Machines Corporation|Method for forming capped copper electrical interconnects|

JP3979687B2|1995-10-26|2007-09-19|アプライドマテリアルズインコーポレイテッド|Method for improving film stability of halogen-doped silicon oxide films|

US6188136B1|1996-06-26|2001-02-13|Kabushiki Kaisha Toshiba|Semiconductor device including a wiring layer having a non-doped or high resistivity polycrystal silicon portion|

US5693563A|1996-07-15|1997-12-02|Chartered Semiconductor Manufacturing Pte Ltd.|Etch stop for copper damascene process|

US6110828A|1996-12-30|2000-08-29|Applied Materials, Inc.|In-situ capped aluminum plug process using selective CVD AL for integrated plug/interconnect metallization|

US5913147A|1997-01-21|1999-06-15|Advanced Micro Devices, Inc.|Method for fabricating copper-aluminum metallization|

US6139697A|1997-01-31|2000-10-31|Applied Materials, Inc.|Low temperature integrated via and trench fill process and apparatus|

US5908813A|1997-02-14|1999-06-01|Micron Technology, Inc.|Method making integrated circuit metallization with superconductor BEOL wiring|

US6139905A|1997-04-11|2000-10-31|Applied Materials, Inc.|Integrated CVD/PVD Al planarization using ultra-thin nucleation layers|

US6387805B2|1997-05-08|2002-05-14|Applied Materials, Inc.|Copper alloy seed layer for copper metallization|

US6605197B1|1997-05-13|2003-08-12|Applied Materials, Inc.|Method of sputtering copper to fill trenches and vias|

US5969422A|1997-05-15|1999-10-19|Advanced Micro Devices, Inc.|Plated copper interconnect structure|

US5897752A|1997-05-20|1999-04-27|Applied Materials, Inc.|Wafer bias ring in a sustained self-sputtering reactor|

US6069068A|1997-05-30|2000-05-30|International Business Machines Corporation|Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity|

US5913145A|1997-08-28|1999-06-15|Texas Instruments Incorporated|Method for fabricating thermally stable contacts with a diffusion barrier formed at high temperatures|

US6042700A|1997-09-15|2000-03-28|Applied Materials, Inc.|Adjustment of deposition uniformity in an inductively coupled plasma source|

US5882498A|1997-10-16|1999-03-16|Advanced Micro Devices, Inc.|Method for reducing oxidation of electroplating chamber contacts and improving uniform electroplating of a substrate|

US5897368A|1997-11-10|1999-04-27|General Electric Company|Method of fabricating metallized vias with steep walls|

KR100273989B1|1997-11-25|2001-01-15|윤종용|Method for forming contact of semiconductor device|

EP1034566A1|1997-11-26|2000-09-13|Applied Materials, Inc.|Damage-free sculptured coating deposition|

US6251528B1|1998-01-09|2001-06-26|International Business Machines Corporation|Method to plate C4 to copper stud|

US6169030B1|1998-01-14|2001-01-02|Applied Materials, Inc.|Metallization process and method|

JP3501937B2|1998-01-30|2004-03-02|富士通株式会社|Method for manufacturing semiconductor device|

US6249055B1|1998-02-03|2001-06-19|Advanced Micro Devices, Inc.|Self-encapsulated copper metallization|

US6281121B1|1998-03-06|2001-08-28|Advanced Micro Devices, Inc.|Damascene metal interconnects using highly directional deposition of barrier and/or seed layers including filling metal|

US6197181B1|1998-03-20|2001-03-06|Semitool, Inc.|Apparatus and method for electrolytically depositing a metal on a microelectronic workpiece|

US6130156A|1998-04-01|2000-10-10|Texas Instruments Incorporated|Variable doping of metal plugs for enhanced reliability|

US6181012B1|1998-04-27|2001-01-30|International Business Machines Corporation|Copper interconnection structure incorporating a metal seed layer|

US6015749A|1998-05-04|2000-01-18|Taiwan Semiconductor Manufacturing Company|Method to improve adhesion between copper and titanium nitride, for copper interconnect structures, via the use of an ion implantation procedure|

US6372633B1|1998-07-08|2002-04-16|Applied Materials, Inc.|Method and apparatus for forming metal interconnects|

US6461675B2|1998-07-10|2002-10-08|Cvc Products, Inc.|Method for forming a copper film on a substrate|

JP3187011B2|1998-08-31|2001-07-11|日本電気株式会社|Method for manufacturing semiconductor device|

US6080285A|1998-09-14|2000-06-27|Applied Materials, Inc.|Multiple step ionized metal plasma deposition process for conformal step coverage|

US6251759B1|1998-10-03|2001-06-26|Applied Materials, Inc.|Method and apparatus for depositing material upon a semiconductor wafer using a transition chamber of a multiple chamber semiconductor wafer processing system|

US6515343B1|1998-11-19|2003-02-04|Quicklogic Corporation|Metal-to-metal antifuse with non-conductive diffusion barrier|

US6187670B1|1998-12-02|2001-02-13|Advanced Micro Devices, Inc.|Multi-stage method for forming optimized semiconductor seed layers|

US6174811B1|1998-12-02|2001-01-16|Applied Materials, Inc.|Integrated deposition process for copper metallization|

US6242349B1|1998-12-09|2001-06-05|Advanced Micro Devices, Inc.|Method of forming copper/copper alloy interconnection with reduced electromigration|

US6261946B1|1999-01-05|2001-07-17|Advanced Micro Devices, Inc.|Method for forming semiconductor seed layers by high bias deposition|

US6258707B1|1999-01-07|2001-07-10|International Business Machines Corporation|Triple damascence tungsten-copper interconnect structure|

EP1149416A1|1999-01-08|2001-10-31|Applied Materials, Inc.|Method of depositing a copper seed layer which promotes improved feature surface coverage|

US6290825B1|1999-02-12|2001-09-18|Applied Materials, Inc.|High-density plasma source for ionized metal deposition|

US6440289B1|1999-04-02|2002-08-27|Advanced Micro Devices, Inc.|Method for improving seed layer electroplating for semiconductor|

US6037258A|1999-05-07|2000-03-14|Taiwan Semiconductor Manufacturing Company|Method of forming a smooth copper seed layer for a copper damascene structure|

US6146517A|1999-05-19|2000-11-14|Infineon Technologies North America Corp.|Integrated circuits with copper metallization for interconnections|

US6147404A|1999-05-24|2000-11-14|Advanced Micro Devices, Inc.|Dual barrier and conductor deposition in a dual damascene process for semiconductors|

US6258223B1|1999-07-09|2001-07-10|Applied Materials, Inc.|In-situ electroless copper seed layer enhancement in an electroplating system|

US6627542B1|1999-07-12|2003-09-30|Applied Materials, Inc.|Continuous, non-agglomerated adhesion of a seed layer to a barrier layer|

US6686280B1|1999-07-22|2004-02-03|Taiwan Semiconductor Manufacturing Company|Sidewall coverage for copper damascene filling|

US6410418B1|1999-08-18|2002-06-25|Advanced Micro Devices, Inc.|Recess metallization via selective insulator formation on nucleation/seed layer|

US6433429B1|1999-09-01|2002-08-13|International Business Machines Corporation|Copper conductive line with redundant liner and method of making|

US6184138B1|1999-09-07|2001-02-06|Chartered Semiconductor Manufacturing Ltd.|Method to create a controllable and reproducible dual copper damascene structure|

US6924226B2|1999-10-02|2005-08-02|Uri Cohen|Methods for making multiple seed layers for metallic interconnects|

US6136707A|1999-10-02|2000-10-24|Cohen; Uri|Seed layers for interconnects and methods for fabricating such seed layers|

US6610151B1|1999-10-02|2003-08-26|Uri Cohen|Seed layers for interconnects and methods and apparatus for their fabrication|

US6395164B1|1999-10-07|2002-05-28|International Business Machines Corporation|Copper seed layer repair technique using electroless touch-up|

US6398929B1|1999-10-08|2002-06-04|Applied Materials, Inc.|Plasma reactor and shields generating self-ionized plasma for sputtering|

US6458251B1|1999-11-16|2002-10-01|Applied Materials, Inc.|Pressure modulation method to obtain improved step coverage of seed layer|

US6387800B1|1999-12-20|2002-05-14|Taiwan Semiconductor Manufacturing Company|Method of forming barrier and seed layers for electrochemical deposition of copper|

US6403465B1|1999-12-28|2002-06-11|Taiwan Semiconductor Manufacturing Company|Method to improve copper barrier properties|

US6395642B1|1999-12-28|2002-05-28|Taiwan Semiconductor Manufacturing Company|Method to improve copper process integration|

US6251242B1|2000-01-21|2001-06-26|Applied Materials, Inc.|Magnetron and target producing an extended plasma region in a sputter reactor|

US6277249B1|2000-01-21|2001-08-21|Applied Materials Inc.|Integrated process for copper via filling using a magnetron and target producing highly energetic ions|

US6225221B1|2000-02-10|2001-05-01|Chartered Semiconductor Manufacturing Ltd.|Method to deposit a copper seed layer for dual damascene interconnects|

US6228759B1|2000-05-02|2001-05-08|Advanced Micro Devices, Inc.|Method of forming an alloy precipitate to surround interconnect to minimize electromigration|

US6368954B1|2000-07-28|2002-04-09|Advanced Micro Devices, Inc.|Method of copper interconnect formation using atomic layer copper deposition|

US6506668B1|2001-06-22|2003-01-14|Advanced Micro Devices, Inc.|Utilization of annealing enhanced or repaired seed layer to improve copper interconnect reliability|

US20030116427A1|2001-08-30|2003-06-26|Applied Materials, Inc.|Self-ionized and inductively-coupled plasma for sputtering and resputtering|

US6936906B2|2001-09-26|2005-08-30|Applied Materials, Inc.|Integration of barrier layer and seed layer|

US6515368B1|2001-12-07|2003-02-04|Advanced Micro Devices, Inc.|Semiconductor device with copper-filled via includes a copper-zinc/alloy film for reduced electromigration of copper|

US7910165B2|2002-06-04|2011-03-22|Applied Materials, Inc.|Ruthenium layer formation for copper film deposition|

US20040140196A1|2003-01-17|2004-07-22|Applied Materials, Inc.|Shaping features in sputter deposition|

US6806192B2|2003-01-24|2004-10-19|Taiwan Semiconductor Manufacturing Company, Ltd.|Method of barrier-less integration with copper alloy|

US6943111B2|2003-02-10|2005-09-13|Taiwan Semiconductor Manufacturing Company, Ltd.|Barrier free copper interconnect by multi-layer copper seed|

US7101790B2|2003-03-28|2006-09-05|Taiwan Semiconductor Manufacturing Co., Ltd.|Method of forming a robust copper interconnect by dilute metal doping|

US20050045485A1|2003-09-03|2005-03-03|Taiwan Semiconductor Manufacturing Co. Ltd.|Method to improve copper electrochemical deposition|

US7265038B2|2003-11-25|2007-09-04|Taiwan Semiconductor Manufacturing Co., Ltd.|Method for forming a multi-layer seed layer for improved Cu ECP|

US7390329B2|2004-05-07|2008-06-24|Usgi Medical, Inc.|Methods for grasping and cinching tissue anchors|

US8828054B2|2008-04-02|2014-09-09|Liavatec Corporation|Method and apparatus for meniscal repair|

US9929006B2|2016-07-20|2018-03-27|Micron Technology, Inc.|Silicon chalcogenate precursors, methods of forming the silicon chalcogenate precursors, and related methods of forming silicon nitride and semiconductor structures|US6482734B1|1998-01-20|2002-11-19|Lg Semicon Co., Ltd.|Diffusion barrier layer for semiconductor device and fabrication method thereof|

JP2000138201A|1998-10-29|2000-05-16|Ulvac Seimaku Kk|Method and system for dry etching of half-tone phase shifted film, half-tone phase shifted photomask and manufacture thereof, and semiconductor circuit and manufacture thereof|

US7105434B2|1999-10-02|2006-09-12|Uri Cohen|Advanced seed layery for metallic interconnects|

US6610151B1|1999-10-02|2003-08-26|Uri Cohen|Seed layers for interconnects and methods and apparatus for their fabrication|

KR100338112B1|1999-12-22|2002-05-24|박종섭|Method of forming a copper wiring in a semiconductor device|

CN1319130C|1999-12-24|2007-05-30|株式会社荏原制作所<Del/>|Apparatus for plating semiconductor substrate, method for plating semiconductor substrate|

US6800554B2|2000-12-18|2004-10-05|Intel Corporation|Copper alloys for interconnections having improved electromigration characteristics and methods of making same|

US8298933B2|2003-04-11|2012-10-30|Novellus Systems, Inc.|Conformal films on semiconductor substrates|

US7842605B1|2003-04-11|2010-11-30|Novellus Systems, Inc.|Atomic layer profiling of diffusion barrier and metal seed layers|

US6764940B1|2001-03-13|2004-07-20|Novellus Systems, Inc.|Method for depositing a diffusion barrier for copper interconnect applications|

US6869515B2|2001-03-30|2005-03-22|Uri Cohen|Enhanced electrochemical depositionfilling of high aspect ratio openings|

US9076843B2|2001-05-22|2015-07-07|Novellus Systems, Inc.|Method for producing ultra-thin tungsten layers with improved step coverage|

US6842659B2|2001-08-24|2005-01-11|Applied Materials Inc.|Method and apparatus for providing intra-tool monitoring and control|

US6936906B2|2001-09-26|2005-08-30|Applied Materials, Inc.|Integration of barrier layer and seed layer|

US6916398B2|2001-10-26|2005-07-12|Applied Materials, Inc.|Gas delivery apparatus and method for atomic layer deposition|

JP3727277B2|2002-02-26|2005-12-14|Ｎｅｃエレクトロニクス株式会社|Manufacturing method of semiconductor device|

US6620724B1|2002-05-09|2003-09-16|Infineon Technologies Ag|Low resistivity deep trench fill for DRAM and EDRAM applications|

US6724087B1|2002-07-31|2004-04-20|Advanced Micro Devices, Inc.|Laminated conductive lines and methods of forming the same|

US6790773B1|2002-08-28|2004-09-14|Novellus Systems, Inc.|Process for forming barrier/seed structures for integrated circuits|

US20040096586A1|2002-11-15|2004-05-20|Schulberg Michelle T.|System for deposition of mesoporous materials|

KR20040060562A|2002-12-30|2004-07-06|동부전자 주식회사|Oxidation prevention method of barrier metal for manufacturing a semiconductor element|

US6806192B2|2003-01-24|2004-10-19|Taiwan Semiconductor Manufacturing Company, Ltd.|Method of barrier-less integration with copper alloy|

US6943111B2|2003-02-10|2005-09-13|Taiwan Semiconductor Manufacturing Company, Ltd.|Barrier free copper interconnect by multi-layer copper seed|

JP4188125B2|2003-03-05|2008-11-26|Ｔｄｋ株式会社|Magnetic recording medium manufacturing method and manufacturing apparatus|

EP1482069A1|2003-05-28|2004-12-01|Interuniversitair Microelektronica Centrum Vzw|Method for producing polycrystalline silicon germanium suitable for micromachining|

US6900127B2|2003-08-27|2005-05-31|Texas Instruments Incorporated|Multilayer integrated circuit copper plateable barriers|

US20050082606A1|2003-10-20|2005-04-21|Stephan Grunow|Low K dielectric integrated circuit interconnect structure|

US7265038B2|2003-11-25|2007-09-04|Taiwan Semiconductor Manufacturing Co., Ltd.|Method for forming a multi-layer seed layer for improved Cu ECP|

KR100587658B1|2003-12-31|2006-06-08|동부일렉트로닉스 주식회사|Termial effect minimizing method in ECP process|

US7732326B2|2004-02-25|2010-06-08|Taiwan Semiconductor Manufacturing Company, Ltd.|Semiconductor device having a second level of metallization formed over a first level with minimal damage to the first level and method|

US20050184288A1|2004-02-25|2005-08-25|Tien-I Bao|Semiconductor device having a second level of metallization formed over a first level with minimal damage to the first level and method|

US7378744B2|2004-05-10|2008-05-27|Taiwan Semiconductor Manufacturing Company, Ltd.|Plasma treatment at film layer to reduce sheet resistance and to improve via contact resistance|

US7067409B2|2004-05-10|2006-06-27|Taiwan Semiconductor Manufacturing Company, Ltd.|Plasma treatment at film layer to reduce sheet resistance and to improve via contact resistance|

US7306962B2|2004-06-17|2007-12-11|Sharp Laboratories Of America, Inc.|Electroformed metallization|

US7112470B2|2004-09-15|2006-09-26|International Business Machines Corporation|Chip dicing|

US20070080455A1|2005-10-11|2007-04-12|International Business Machines Corporation|Semiconductors and methods of making|

US7863183B2|2006-01-18|2011-01-04|International Business Machines Corporation|Method for fabricating last level copper-to-C4 connection with interfacial cap structure|

US7645696B1|2006-06-22|2010-01-12|Novellus Systems, Inc.|Deposition of thin continuous PVD seed layers having improved adhesion to the barrier layer|

EP1909320A1|2006-10-05|2008-04-09|ST Microelectronics Crolles 2 SAS|Copper diffusion barrier|

US7510634B1|2006-11-10|2009-03-31|Novellus Systems, Inc.|Apparatus and methods for deposition and/or etch selectivity|

KR100763136B1|2006-12-11|2007-10-02|동부일렉트로닉스 주식회사|Wafer bonding method in system-in-package|

DE102007004884A1|2007-01-31|2008-08-14|Advanced Micro Devices, Inc., Sunnyvale|A method of forming a metal layer over a patterned dielectric by electroless deposition using a selectively provided activation layer|

US8058164B2|2007-06-04|2011-11-15|Lam Research Corporation|Methods of fabricating electronic devices using direct copper plating|

JP2009016520A|2007-07-04|2009-01-22|Tokyo Electron Ltd|Method and apparatus for manufacturing semiconductor apparatus|

US8084862B2|2007-09-20|2011-12-27|International Business Machines Corporation|Interconnect structures with patternable low-k dielectrics and method of fabricating same|

US7709370B2|2007-09-20|2010-05-04|International Business Machines Corporation|Spin-on antireflective coating for integration of patternable dielectric materials and interconnect structures|

US8618663B2|2007-09-20|2013-12-31|International Business Machines Corporation|Patternable dielectric film structure with improved lithography and method of fabricating same|

US20090127097A1|2007-11-16|2009-05-21|Kei-Wei Chen|Forming Seed Layer in Nano-Trench Structure Using Net Deposition and Net Etch|

KR100924556B1|2008-01-04|2009-11-02|주식회사 하이닉스반도체|Metal wiring of semiconductor device and method of manufacturing the same|

US7704886B2|2008-02-14|2010-04-27|Taiwan Semiconductor Manufacturing Company, Ltd.|Multi-step Cu seed layer formation for improving sidewall coverage|

US8252690B2|2008-02-14|2012-08-28|Taiwan Semiconductor Manufacturing Company, Ltd.|In situ Cu seed layer formation for improving sidewall coverage|

US7879720B2|2008-09-30|2011-02-01|Samsung Electronics Co., Ltd.|Methods of forming electrical interconnects using electroless plating techniques that inhibit void formation|

US9159571B2|2009-04-16|2015-10-13|Lam Research Corporation|Tungsten deposition process using germanium-containing reducing agent|

US20100267230A1|2009-04-16|2010-10-21|Anand Chandrashekar|Method for forming tungsten contacts and interconnects with small critical dimensions|

US10381266B2|2012-03-27|2019-08-13|Novellus Systems, Inc.|Tungsten feature fill with nucleation inhibition|

US10256142B2|2009-08-04|2019-04-09|Novellus Systems, Inc.|Tungsten feature fill with nucleation inhibition|

US7956463B2|2009-09-16|2011-06-07|International Business Machines Corporation|Large grain size conductive structure for narrow interconnect openings|

JP5498751B2|2009-10-05|2014-05-21|ルネサスエレクトロニクス株式会社|Manufacturing method of semiconductor device|

US8900663B2|2009-12-28|2014-12-02|Gvd Corporation|Methods for coating articles|

US9714474B2|2010-04-06|2017-07-25|Tel Nexx, Inc.|Seed layer deposition in microscale features|

US8993434B2|2010-09-21|2015-03-31|Applied Materials, Inc.|Methods for forming layers on a substrate|

US8524599B2|2011-03-17|2013-09-03|Micron Technology, Inc.|Methods of forming at least one conductive element and methods of forming a semiconductor structure|

JP2012231096A|2011-04-27|2012-11-22|Elpida Memory Inc|Semiconductor device and manufacturing method of the same|

US8525339B2|2011-07-27|2013-09-03|International Business Machines Corporation|Hybrid copper interconnect structure and method of fabricating same|

US8946082B2|2011-09-16|2015-02-03|GlobalFoundries, Inc.|Methods for forming semiconductor devices|

KR102064627B1|2012-03-27|2020-01-09|노벨러스 시스템즈, 인코포레이티드|Tungsten feature fill|

US20140046475A1|2012-08-09|2014-02-13|Applied Materials, Inc.|Method and apparatus deposition process synchronization|

US8853080B2|2012-09-09|2014-10-07|Novellus Systems, Inc.|Method for depositing tungsten film with low roughness and low resistivity|

US8729702B1|2012-11-20|2014-05-20|Stmicroelectronics, Inc.|Copper seed layer for an interconnect structure having a doping concentration level gradient|

US9153486B2|2013-04-12|2015-10-06|Lam Research Corporation|CVD based metal/semiconductor OHMIC contact for high volume manufacturing applications|

US9589808B2|2013-12-19|2017-03-07|Lam Research Corporation|Method for depositing extremely low resistivity tungsten|

US9349637B2|2014-08-21|2016-05-24|Lam Research Corporation|Method for void-free cobalt gap fill|

US9748137B2|2014-08-21|2017-08-29|Lam Research Corporation|Method for void-free cobalt gap fill|

US9997405B2|2014-09-30|2018-06-12|Lam Research Corporation|Feature fill with nucleation inhibition|

US9953984B2|2015-02-11|2018-04-24|Lam Research Corporation|Tungsten for wordline applications|

US10170320B2|2015-05-18|2019-01-01|Lam Research Corporation|Feature fill with multi-stage nucleation inhibition|

US9613818B2|2015-05-27|2017-04-04|Lam Research Corporation|Deposition of low fluorine tungsten by sequential CVD process|

US9754824B2|2015-05-27|2017-09-05|Lam Research Corporation|Tungsten films having low fluorine content|

US9978605B2|2015-05-27|2018-05-22|Lam Research Corporation|Method of forming low resistivity fluorine free tungsten film without nucleation|

US9754891B2|2015-09-23|2017-09-05|International Business Machines Corporation|Low-temperature diffusion doping of copper interconnects independent of seed layer composition|

US9735051B2|2015-12-14|2017-08-15|International Business Machines Corporation|Semiconductor device interconnect structures formed by metal reflow process|

BR112018009258A2|2016-02-05|2018-11-06|Board Of Regents Of The University Of Texas System|medical device, method for preparing a tubular-shaped polymer electrolyte layer and method for preparing an ionic electroactive polymer driver|

US10573522B2|2016-08-16|2020-02-25|Lam Research Corporation|Method for preventing line bending during metal fill process|

US9852990B1|2016-08-17|2017-12-26|International Business Machines Corporation|Cobalt first layer advanced metallization for interconnects|

US9941212B2|2016-08-17|2018-04-10|International Business Machines Corporation|Nitridized ruthenium layer for formation of cobalt interconnects|

US10115670B2|2016-08-17|2018-10-30|International Business Machines Corporation|Formation of advanced interconnects including set of metal conductor structures in patterned dielectric layer|

US9859215B1|2016-08-17|2018-01-02|International Business Machines Corporation|Formation of advanced interconnects|

US9716063B1|2016-08-17|2017-07-25|International Business Machines Corporation|Cobalt top layer advanced metallization for interconnects|

US10211099B2|2016-12-19|2019-02-19|Lam Research Corporation|Chamber conditioning for remote plasma process|

US11195748B2|2017-09-27|2021-12-07|Invensas Corporation|Interconnect structures and methods for forming same|

US10937960B2|2018-08-14|2021-03-02|Newport Fab, Llc|Concurrent fabrication of and structure for capacitive terminals and ohmic terminals in a phase-change materialradio frequencyswitch|

法律状态:
2003-01-23| STCF| Information on status: patent grant|Free format text: PATENTED CASE |

2006-08-09| FPAY| Fee payment|Year of fee payment: 4 |

2010-01-22| AS| Assignment|Owner name: SEED LAYERS TECHNOLOGY LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:COHEN, URI;REEL/FRAME:023832/0471 Effective date: 20100121 Owner name: SEED LAYERS TECHNOLOGY LLC,NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:COHEN, URI;REEL/FRAME:023832/0471 Effective date: 20100121 |

2010-07-26| FPAY| Fee payment|Year of fee payment: 8 |

2012-12-06| AS| Assignment|Owner name: COHEN, URI, DR., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SEED LAYER TECHNOLOGY, LLC;REEL/FRAME:029420/0866 Effective date: 20121205 |

2014-08-05| FPAY| Fee payment|Year of fee payment: 12 |

2018-02-20| IPR| Aia trial proceeding filed before the patent and appeal board: inter partes review|Free format text: TRIAL NO: IPR2018-00467 Opponent name: APPLIED MATERIALS, INC., TAIWAN SEMICONDUCTOR MANU Effective date: 20180115 Free format text: TRIAL NO: IPR2018-00448 Opponent name: APPLIED MATERIALS, INC., TAIWAN SEMICONDUCTOR MANU Effective date: 20180115 |

2018-04-03| IPR| Aia trial proceeding filed before the patent and appeal board: inter partes review|Free format text: TRIAL NO: IPR2018-00449 Opponent name: APPLIED MATERIALS, INC., TAIWAN SEMICONDUCTOR MAN Effective date: 20180115 |

2018-04-10| IPR| Aia trial proceeding filed before the patent and appeal board: inter partes review|Free format text: TRIAL NO: IPR2018-00730 Opponent name: APPLIED MATERIALS, INC.,TAIWAN SEMICONDUCTOR MANUF Effective date: 20180306 |

2018-05-15| IPR| Aia trial proceeding filed before the patent and appeal board: inter partes review|Free format text: TRIAL NO: IPR2018-00724 Opponent name: APPLIED MATERIALS, INC., TAIWAN SEMICONDUCTOR MANU Effective date: 20180306 Free format text: TRIAL NO: IPR2018-00723 Opponent name: APPLIED MATERIALS, INC., TAIWAN SEMICONDUCTOR MANU Effective date: 20180306 |

优先权:

申请号 | 申请日 | 专利标题

US09/410,898|US6136707A|1999-10-02|1999-10-02|Seed layers for interconnects and methods for fabricating such seed layers|

US09/563,733|US6610151B1|1999-10-02|2000-05-03|Seed layers for interconnects and methods and apparatus for their fabrication|

US09/730,220|US6518668B2|1999-10-02|2000-12-04|Multiple seed layers for metallic interconnects|US09/730,220| US6518668B2|1999-10-02|2000-12-04|Multiple seed layers for metallic interconnects|

US10/328,629| US6924226B2|1999-10-02|2002-12-23|Methods for making multiple seed layers for metallic interconnects|

US11/023,833| US7105434B2|1999-10-02|2004-12-28|Advanced seed layery for metallic interconnects|

US11/391,035| US7682496B2|1999-10-02|2006-03-28|Apparatus for depositing seed layers|

US12/728,393| US8123861B2|1999-10-02|2010-03-22|Apparatus for making interconnect seed layers and products|

US13/352,180| US8586471B2|1999-10-02|2012-01-17|Seed layers for metallic interconnects and products|

US14/077,058| US20140061919A1|1999-10-02|2013-11-11|Electroplated Metallic Interconnects And Products|

US14/619,334| US10096547B2|1999-10-02|2015-02-11|Metallic interconnects products|

[返回顶部]